Ville : Ottawa, Ontario, Canada

Catégorie : Engineering

Industrie : Telecommunications

Employeur : Ciena

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

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Why Ciena:

• You will be a member of a successful team working on the forefront of technological innovation focused on leading edge technologies, flows and products.  You will be working with, and learning from, industry recognized experts.
• Our team supports an inclusive, diverse and barrier-free work environment making for empowered and committed employees.
• We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families.
• Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.

How You Will Contribute:

The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. Reporting to Senior Manager, as a Senior Digital Design Engineer, you will be asked to propose innovative solutions in order to design power and area-optimized functional blocks for the Wavelogic family of products.

• You will read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.
• You will produce an implementation specification document and have it reviewed by your team, architects, and analog designers, if applicable
• You will be accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions.
• You will be responsible for designer testing of your code as well as debugging of your code during simulation and regression verification.
• You will assist the verification team in determining coverage and provide design assertions and waivers as needed.
• You will craft timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews.

What Does Ciena Expect of You:

• Sense of urgency and accountability – what’s important to the customer is important to you; you make getting things done a priority.
• Detail-oriented – you will deliver on objectives through meticulous, thorough, and comprehensive work.
• Problem solver – you possess the ability to analyze and methodically solve complex technical problems using engineering principles and approaches.
• Commitment to learning – you keep abreast of technology developments and are keen to share your knowledge with others.

The Must Haves:

• Minimum Bachelors degree in Electrical or Computer Engineering, Computer Science coupled with proven experience in the use of System Verilog for design.
• Familiarity with digital (including formal) verification methods.
• Experience with digital design synthesis, STA, timing closure and asynchronous clock crossing.
• Good understanding of timing/power/area analysis and trade-offs.

Assets:

• Experience with
  • digital silicon design backend process.
  • digital design for low power.
  • DSP and/or Forward Error Correction
  • Using Jira for bug tracking and GIT for source code management and revision tracking
• Familiarity with programming languages such as: Python, C, C++