Senior Digital Verification Engineer (FEC)
City : Ottawa
Category : Engineering
Industry : Telecommunications
Employer : Ciena
Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
You will be a member of a successful team working on the forefront of technological innovation focused on leading edge technologies, flows and products. You will be working with, and learning from, industry recognized experts.
Our team supports an inclusive, diverse and barrier-free work environment making for empowered and committed employees.
We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families.
Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.
How You Will Contribute:
The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. Reporting to ASIC Senior Manager, as a Senior Digital Verification Engineer, in conjunction with a team of Digital Design Engineers, Verification Engineers and Architects, you’ll play a key role in implementing innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Forward Error Correction block (FEC).
You will read and understand the FEC architecture and functional requirements specification document(s).
You will communicate and collaborate with FEC designers, DSP modelers, FEC verifiers, systems engineers and architects.
You will be responsible for completing and thorough validation of one or more FEC functional blocks by using an appropriate combination of simulation, formal and coverage methods.
You will create the verification, functional coverage and formal verification test plans.
You will be accountable for the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your FEC functional block using System Verilog UVM and C++.
You will perform coverage driven verification, monitor regressions and debug resulting failures with the help of the function's designer and provide status updates on a regular basis.
What Does Ciena Expect of You:
Sense of urgency and accountability – what’s important to the customer is important to you; you make getting things done a priority.
Detail-oriented – you will deliver on objectives through meticulous, thorough, and comprehensive work.
Problem solver – you possess the ability to analyze and methodically solve complex technical problems using engineering principles and approaches.
Commitment to learning – you keep abreast of technology developments and are keen to share your knowledge with others.
The Must Haves:
Minimum Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with significant experience in the use of System Verilog, UVM, SVA, C++, and simulators from major vendors.
Proven ability in determining appropriate and comprehensive digital verification and coverage strategies.
Experience with formal verification methods.
Strong background in Forward Error Correction (FEC) and/or DSP.
Using Jira for bug tracking.
GIT for source code management and revision tracking
Familiarity with various programming languages such as: Python, Make, bash, and object-oriented programming.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.